Fail analysis device

ABSTRACT

A fail analysis device enabling a simplified operation and a reduced operation time.. A reduced data acquiring section ( 40 ) reads a reduced logical data, obtained by reducing detailed logical data as a test result, from a CFM ( 120 ) in a semiconductor test device ( 100 ) and acquires it. A main viewer generating section ( 80 ) generates a main viewer window including a list of a test result for each DUT based on the reduced logical data for displaying on a display device ( 94 ). The list includes a result image indicating a pass/fail for each DUT and the reduced image of a fail bit map.

TECHNICAL FIELD

[0001] The present invention relates to a fail analysis device fordisplaying a measurement result of a fail distribution state of storagecells of a semiconductor memory.

BACKGROUND ART

[0002] A semiconductor test device performs reading and writing of datawith respect to each storage cell in a semiconductor memory (hereinaftersimply referred to as “memory”) serving as a device to be tested (DUT),thereby analyzing failure of each storage cell. In general, thesemiconductor test device compares data read out from the DUT andpredetermined expected value data to perform judgment of pass/fail andstores a result of this judgment in a fail memory. Fail informationstored in the fail memory in this way is collected by a fail analysisdevice constituted by a workstation and the like to investigate contentsof the information, whereby various kinds of failure analysis withrespect to this DUT is performed.

[0003] For example, the fail analysis device can display a faildistribution state of a large capacity DRAM as a physical map or alogical map by using a predetermined memory device evaluation tool. Thephysical map is a two-dimensional fail bit map using physical addressesX and Y as coordinates and is used for confirming a physical arrangementof failure storage cells of a memory. In addition, the logical map is athree-dimensional fail bit map using logical addresses X and Y and anI/O number as coordinates and may be four-dimensional in the case inwhich a logical address Z is used. This logical map is generated basedupon fail information to be read out from the above-described failmemory.

[0004] Incidentally, a general semiconductor test device is capable ofperforming tests for a plurality of memories simultaneously, therebyrealizing reduction of a test time for one memory. Therefore, when onetest ends, fail information corresponding to each of the plurality ofmemories is stored in the above-described fail memory.

[0005] However, if a user attempts to cause the conventional failanalysis device to display contents of the logical map or the physicalmap in order to analyze the fail information obtained in this way, theuser needs to specify a DUT in the first place. Therefore, in the casein which the user desires to know an outline of the fail information forthe plurality of DUT which was objects of the test, the user needs to,after designating one DUT, repeat an operation for displaying contentsthereof for each DUT. Thus, there is a problem in that complicatedoperations are necessary, operability is poor, and long time is requiredfor the operations.

[0006] In particular, in the case in which the user displays contents ofthe logical map, the user needs to specify an I/O number together with aDUT. Therefore, in the case in which the user desires to look at anoutline of fail information for one DUT, the user needs to,afterdesignating one I/O number, repeat an operation for displaying contentsthereof for each I/O number. Thus, operations become more complicatedand long time is required for the operations.

[0007] In addition, since the user can only display contents of thephysical map or the logical map by designating a DUT and the I/O numberin the conventional fail analysis device as described above, when theuser attempts to compare fail information of the respective DUTs forwhich the test was performed simultaneously or compare fail informationof each I/O number of one DUT, the user needs to remember contents ofeach physical map or each logical map to be an object of comparison orto print the contents in a paper or the like. Thus, there is a problemin that it is not easy to grasp an outline of fail information for aplurality of DUTs or grasp an outline of fail information for aplurality of I/O numbers of each DUT.

[0008] In addition, in the above-described conventional fail analysisdevice, a detailed logical map or physical map is displayed byperforming physical conversion processing based upon fail informationread out from the fail memory in the semiconductor test device or usingthis fail information. Thus, in the case in which the user moves orenlarges a range of a logical map or a physical map to be an object ofdisplay, the user needs to read out the fail information from the failmemory in the semiconductor test device again. Therefore, there is aproblem in that long time is required since the user instructs change ofa display range until the display range is actually changed.

[0009] In addition, in the conventional fail analysis device, there is aproblem in that an operation for instructing change of a display rangeis not easy and operability is poor. For example, in the case in which areduced display screen containing a fail bit map corresponding to theentire DUT and a detailed display screen containing a detailed fail bitmap corresponding to a part of the DUT can be selectively switched to bedisplayed, after confirming a detailed fail bit map of which part theuser desires to look at with the reduced display screen, the userswitches to a screen of this detailed fail bit map. In this case, if theuser attempts to look at detailed fail bit maps of the other parts, theuser needs to switch to the reduced display screen again. An operationbecomes complicated because the user needs to switch the screens manytimes. In addition, although it is possible to display a detailed failbit map of a part, which the user desires to look at, by scrollingdisplayed contents of the detailed display screen, the contents is notconfirmed by alternately displaying the reduced display screen and thedetailed display screen. Thus, it is not easy to find a fail part, whichthe user desires to look at next, by the scroll operation, and thescroll operation is repeated carelessly to some extent.

[0010] In addition, it is convenient if the logical map or the physicalmap generated by the above-described conventional fail analysis devicecan be superimposed with each other in the case in which tendencies offail are compared, or the like. In the conventional fail analysisdevice, such superimposition of a plurality of bit maps is impossible,or it is possible only to perform simple superimposition underlimitation. For example, even in the case in which superimposition oftwo fail bit maps is possible, these two fail bit maps are notassociated with each other. Thus, if the user desires to performsuperimposition by changing a display magnification again, the userneeds to change the display magnification for each of the two fail bitmaps. In addition, in the case in which the user desires to move adisplay area of the fail bit maps, since the two fail bit maps do notmove in association with each other, the user needs to move the displayarea for each of the two fail bit maps. In addition, in the case inwhich the user performs superimposition by changing a combination of theplurality of fail bit maps, operations are repeated from reading of datafor all the fail bit maps to be objects of superimposition every timethe combination is changed. In addition, in the case in which theplurality of fail bit maps are superimposed, since only an order ofsuperimposing them cannot be changed, a fail bit map is redrawn bychanging the order. In this way, in the case in which superimposition offail bit maps is performed using the conventional fail analysis device,there is a problem in that operations in performing some kind of changebecome complicated.

[0011] Further, in the case in which, for example, when two fail bitmaps are compared, the user confirms to which degree fail parts coincidewith each other, the user needs to perform an arithmetic operation ofsuperimposed fail bit maps. However, in the conventional fail analysisdevice, it is impossible to perform such an arithmetic operation of failbit maps.

DISCLOSURE OF THE INVENTION

[0012] The present invention has been devised in view of such point, andit is an object of the present invention to provide a fail analysisdevice enabling a simplified operation and a reduced operation time. Inaddition, it is another object of the present invention to provide afail analysis device with which an outline of fail information isgrasped easily. Further, it is another object of the present inventionto provide a fail analysis device which can perform an arithmeticoperation using a superimposed plurality of bit maps.

[0013] The fail analysis device of the present invention is a device fordisplaying results of testing a plurality of semiconductor memories witha semiconductor test device, and is provided with a test resultacquiring unit for acquiring test results corresponding to the pluralityof semiconductor memories, a list image generation unit for generating alist image in which the test results corresponding to the plurality ofsemiconductor memories, which are acquired by this test result acquiringunit, are included in one screen, and a display unit for displaying thelist image generated by this list image generation unit. Since the testresults corresponding to the plurality of semiconductor memories aredisplayed in one screen, it becomes easy to grasp an outline of failinformation for each semiconductor memory.

[0014] More specifically, it is desirable that a result image, whichindicates pass/fail for each of the plurality of semiconductor memories,is included as the test result in the above-described list image.Alternatively, it is desirable that a reduced image of a fail bit map isincluded as the test result for each of the plurality of semiconductormemories in the above-described list image. Since a user can learnwhether or not a fail part is included in each semiconductor memory orcan learn a general state of a fail distribution of each semiconductormemory by looking at the result image, the user can surely grasp anoutline of fail information for the entire plurality of semiconductormemories.

[0015] In addition, the fail analysis device of the present invention isa device for displaying a result of testing a semiconductor memory witha semiconductor test device, and is provided with a test resultacquiring unit for acquiring a test result corresponding to thesemiconductor memory, a list image generation unit for generating a listimage in which a test result for each I/O number of the semiconductormemory, which is acquired by this test result acquiring unit, isincluded in one screen, and a display unit for displaying the list imagegenerated by the list image generation unit. Since the test resultcorresponding to a plurality of I/O numbers included in thesemiconductor memory is displayed on one screen, it becomes easy tograsp an outline of fail information corresponding to each I/O number.

[0016] More specifically, it is desirable that a result image indicatingpass/fail is included for each I/O number in the above-described listimage as the test result. Alternatively, it is desirable that a reducedimage of a fail bit map is included for each I/O number in theabove-described list image as the test result. Since a user can learnwhether or not a fail part is included in a fail bit map correspondingto each I/O number or can learn general contents of the fail bit mapcorresponding to each I/O number when the user looks at the list image,the user can surely grasp an outline of fail information for the entireplurality of I/O numbers of the semiconductor memory.

[0017] In addition, it is desirable that the fail analysis device isfurther provided with an operation unit for designating any position inthe list image displayed on the above-described display unit and adetailed image generation unit for, when any result image is designatedby this operation unit, generating a detailed image of a fail bit mapcorresponding to the result image. It is possible that detailed contentscorresponding to the result image can be displayed simply by designatingany of result images included in the list image. Therefore, troublesomelabors, which are required until contents of a detailed fail bit mapcorresponding to a semiconductor memory including the fail part or anI/O number are confirmed, are reduced, and simplification of operationsbecomes possible. In addition, following the simplification ofoperations, reduction of an operation time also becomes possible.

[0018] In addition, it is desirable that the fail analysis device isfurther provided with an operation unit for designating any position inthe list image displayed on the above-described display unit and adetailed image generation unit for, when any reduced image is designatedby this operation unit, generating a detailed image of a fail bit mapcorresponding to the reduced image. It is possible that detailedcontents corresponding to the reduced image can be displayed simply bydesignating any of a plurality of reduced images included in the listimage. Consequently, in the case in which a user would like to confirmthe detailed contents after he/she look over the reduced display,troublesome labors, which are required until contents of a detailed failbit map corresponding to a semiconductor memory or an I/O number areconfirmed, are reduced, and simplification of operations becomespossible. In addition, following the simplification of operations,reduction of an operation time also becomes possible.

[0019] In addition, it is desirable that a reduced fail bit map datanecessary for displaying the reduced image is generated by theabove-described semiconductor test device and generation of the reducedimage is performed by the list image generation unit based upon thisreduced fail bit map data. Since the reduced fail bit map data isgenerated by the semiconductor test device, the fail analysis device canread this generated reduced fail bit map data to generate the reducedimage. Therefore, compared with the case in which a detailed fail bitmap data is read by the fail analysis device and subjected topredetermined reduction processing to generate a reduced image, timerequired for reading of data necessary for generation of a list imagecan be reduced, and reduction of time until the list image is displayedbecomes possible.

[0020] In addition, in the case in which a result of testing asemiconductor memory with a semiconductor test device is displayed, thefail analysis device of the present invention is provided with a testresult acquiring unit for acquiring a test result of the semiconductormemory enabling generation of a fail bit map of a first range, a failbit map generation unit for generating an image of a fail bit map of asecond range narrower than the first range using a part of the testresult acquired by the test result acquiring unit, a display unit fordisplaying the image generated by the fail bit map generation unit, anoperation unit for instructing a display range of the fail bit map, anda display range changing unit for changing the display range using thetest result acquired by the test result acquiring unit when change ofthe display range is instructed within the first range by the operationunit. Since the range for acquiring the test result is set to the firstrange wider than the second range which is a display range, the userdoes not need to acquire the test result again when this display rangeis changed within the first range. Therefore, time required since thechange of the display range is instructed until the display range isactually changed can be reduced.

[0021] In addition, it is desirable that the fail analysis device isprovided with an acquisition range setting unit for variably setting asize of the first range according to a size of the display rangeinstructed by the above-described operation unit If the display range islarge, the acquisition range of a test result is set large and, to thecontrary, if the display range is small, the acquisition range of a testresult is set small. Thus, waste of acquiring a test result even for arange almost unnecessary for display can be cut down, and a displayoperation taking into account processing capability and the like becomespossible.

[0022] In addition, it is desirable that the above-described test resultacquiring unit performs reacquisition of the test result of thesemiconductor memory when change of the display range exceeding thefirst range is instructed by the operation unit. Consequently, thenumber of times of acquiring the test result can be minimized.

[0023] Further, in the case in which a result of testing a semiconductormemory with a semiconductor test device is displayed, the fail analysisdevice of the present invention is provided with a test result acquiringunit for acquiring a test result of the semiconductor memory, a fail bitmap generation unit for generating a first image of a fail bit map and asecond image which is a reduced image of predetermined range includingthe vicinity of this first image using the test result acquired by thetest result acquiring unit, a display unit for displaying the firstimage and the second image in one screen, an operation unit forinstructing change of a display range of a fail bit map corresponding tothe first image using the second image, and a display range changingunit for changing displayed contents of the first image when change ofthe display range is instructed by the operation unit. Since a reducedimage (second image) and a detailed image (first image) are included inan identical screen and change of the display range can be instructedusing this reduced image, a user does not need to switch to a detaileddisplay screen after roughly confirming contents on a reduced displayscreen as in the past, and operability in giving an instruction ofswitching can be improved.

[0024] Moreover, it is desirable that the above-described operation unitis a pointing device capable of designating an arbitrary position of thedisplay screen, and by designating two points in the second image withthis pointing device, a rectangular area with these two points asopposite angles is designated as a display range after it has beenchanged. Alternatively, it is desirable that the above-describedoperation unit is a pointing device capable of designating an arbitraryposition on the display screen, and after one point in the second imageis designated with this pointing device, by designating a movingdirection and a moving amount thereof, move of the display range isinstructed. Since a user can perform designation of a new display rangeby designating two points in the second image larger than the displayrange of the detailed fail bit map, designation of a range of zoom-in orzoom-out can be performed simply and with the same operation procedures.In addition, by designating one point in the second image and a movingdirection and a moving amount thereof, since the user can performdesignation of a new display range, an instruction to move the displayrange can be given easily.

[0025] In addition, it is desirable that an acquisition frame indicatinga range of the test result acquired by the test result acquiring unitand a display frame indicating a drawing range of the first image areincluded in the above-described second image. Since a user can performdesignation of change of the display range while confirming an actualdisplay range, it becomes easy to judge which part is made a displayrange next, and a desired part can be displayed with a fewer number ofoperation times. In addition, since the user can perform designation ofchange of the display range while confirming an acquisition range of thetest result, it becomes possible to instruct change of the display rangewithin the acquisition range of the test result.

[0026] In addition, it is desirable that the above-described test resultacquiring unit performs reacquisition of the test result of thesemiconductor memory when change of the display range exceeding theacquisition frame is instructed by the operation unit. In the case inwhich the display range is changed within the range of the acquisitionrange, since a user does not need to perform reacquisition of the testresult, the number of times of reacquisition of the test result can bereduced, and time required for changing the display range can bereduced.

[0027] In addition, in the case in which a result of testing asemiconductor memory with a semiconductor test device is displayed, thefail analysis device of the present invention is provided with a failbit map generation unit for generating a plurality of fail bit mapimages representing a test result corresponding to the semiconductormemory, a layer control unit for assigning each of the plurality of failbit map images to a plurality of layers and defining relationship amongthe respective layers, an image superimposing unit for performingprocessing for superimposing the plurality of fail bit map imagesdefined the relationship among the plurality of layers by the layercontrol unit, and a display unit for displaying the images superimposedby the image superimposing unit. Since each of the superimposedplurality of fail bit map images corresponds to the plurality of layersand the relationship among the respective layers is defined, in the casein which change of contents of the display image is performed, forexample, in the case in which a display magnification is changed or adisplay range is moved, a user can change displayed contents whilekeeping a mutual relation of the respective fail bit map image.Consequently, the user does not need to give an instruction to move therespective fail bit map image individually or give an instruction tochange a display magnification, and operations can be simplifiedsignificantly.

[0028] In addition, it is desirable that the above-described layercontrol unit controls a display/non-display state of a fail bit mapimage for each layer. Consequently, when display of each of thesuperimposed fail bit map is turned off or the fail bit map isre-displayed, it becomes unnecessary to repeat reading of data ordrawing processing each time, and simplification of processing andoperations becomes possible.

[0029] In addition, it is desirable that the above-described layercontrol unit sets contents of a logical operation targeting each of theplurality of layers according to the relation. Since contents of thelogical operation are set when the relationship among the respectivelayers is defined, a logical operation targeting each fail bit mapbecomes possible in accordance with the set contents.

[0030] In addition, it is desirable that the fail analysis device isfurther provided with an operation unit for instructing change of adisplay range of the above-described fail bit map and a display rangechanging unit for, when change of the display range is instructed bythis operation unit, executing change of the display range targeting theplurality of fail bit maps corresponding to the plurality of layersassigned by the layer control unit. Consequently, by giving aninstruction of change once by the operation unit, a user can changedisplay ranges of a plurality of fail bit maps simultaneously.

[0031] Further, it is desirable that the above-described layer controlunit defines the relationship by assigning images including images notrelating to the test result other than the plurality of fail bit mapimages to each of the plurality of layers. For example, in the case inwhich images such as a predetermined frame, ruled lines, letters, or thelike are considered, legibility or the like of displayed contents can beimproved by further adding this image to the superimposed plurality offail bit map images.

BRIEF DESCRIPTION OF THE DRAWINGS

[0032]FIG. 1 is a diagram showing a structure of a semiconductor testdevice to which a fail analysis device of an embodiment is connected;

[0033]FIG. 2 is a diagram showing a detailed structure of the failanalysis device of this embodiment;

[0034]FIG. 3 is a flow diagram showing operation procedures of a failanalysis device corresponding to a specific example 1;

[0035]FIG. 4 is a diagram showing a specific example of a main viewerwindow to be displayed after the fail analysis device is started up;

[0036]FIG. 5 is a diagram showing a specific example of a main viewerwindow in which a list of reduced images indicating reduced logical mapsis included;

[0037]FIG. 6 is a diagram showing another specific example of the mainviewer window;

[0038]FIG. 7 is a diagram showing a specific example of a logical viewerwindow;

[0039]FIG. 8 is a diagram showing a specific example of a physicalviewer window;

[0040]FIG. 9 is a flow diagram showing operation procedures of a failanalysis device corresponding to a specific example 2;

[0041]FIG. 10 is a diagram showing a specific example of a page sizemenu;

[0042]FIG. 11 is a diagram showing a relation between a display rangeand an acquisition range of data;

[0043]FIG. 12 is a diagram showing a specific example of an instructionof move using a reduced logical map;

[0044]FIG. 13 is a diagram showing a specific example of instruction ofzoom using the reduced logical map;

[0045]FIG. 14 is a flow diagram showing operation procedures of a failanalysis device corresponding to a specific example 3;

[0046]FIG. 15 is a diagram showing a specific example of a layer window;

[0047]FIG. 16 is a diagram showing a specific example of superimpositionof fail bit maps;

[0048]FIG. 17 is a diagram showing another specific example ofsuperimposition of fail bit maps;

[0049]FIG. 18 is a diagram showing another specific example ofsuperimposition of fail bit maps;

[0050]FIG. 19 is a diagram showing another specific example ofsuperimposition of fail bit maps; and

[0051]FIG. 20 is a diagram showing another specific example ofsuperimposition of fail bit maps.

BEST MODE FOR CARRYING OUT THE INVENTION

[0052] A fail analysis device of an embodiment to which the presentinvention is applied will be hereinafter described with reference to theaccompanying drawings.

[0053]FIG. 1 is a diagram showing a structure of a semiconductor testdevice to which a fail analysis device of this embodiment is connected.As shown in FIG. 1, a semiconductor test device 100 includes a timinggenerator 110, a pattern generator 112, a waveform shaper 114, a logiccomparator 116, an AFM (address fail memory) 118, a CFM (compact failmemory) 120, a tester processing section 122, a communication controlsection 124, and a physical conversion section 126.

[0054] An address and data generated by the pattern generator 112 iswaveformshaped by the waveform shaper 114 and inputted to the DUT 130.The logic comparator 116 compares data read out from the DUT 130 and anexpected value to be outputted from the pattern generator 112 to performjudgment of pass/fail.

[0055] The AFM 118 stores fail information for each address according toa fail signal to be outputted by the logic comparator 116 and an addresssignal to be outputted by the pattern generator 112. All of these seriesof operations are performed synchronous with a system clock to beinputted in each section from the timing generator 110. The failinformation to be stored in this AFM 118 is logic fail bit map data, andbit data indicating pass/fail for each storage cell specified by an Xaddress and a Y address for each I/O number (e.g., pass corresponds to“0” and fail corresponds to “1”) is stored.

[0056] In addition, the CFM 120 stores fail information which is reducedcontent of the AFM 118. For example, for each I/O number, the X addressis divided into n and the Y address is divided into m, and one bit datacorresponding to each divided area is obtained. More specifically, avalue of this one bit data is found by calculating OR of a plurality ofbit data of the AFM 118 corresponding to the divided areas of the Xaddress and the divided areas of the Y address. That is, in the case inwhich at least one “1” indicating fail is included in the plurality ofbit data specified by each divided area, corresponding bit data in theCFM 120 is set to “1” indicating fail. In the case in which all theplurality of bit data specified by each divided area is “0” indicatingpass, corresponding bit data in the CFM 120 is set to “0” indicatingpass. Note that, in the following description, data read out from theAFM 118 is referred to as “AFM data” or “detailed logical data” and dataread out from the CFM 120 is referred to as “CFM data” or “reducedlogical data” for the description.

[0057] The physical conversion section 126 performs physical conversionprocessing based upon the detailed logical data stored in the AFM 118,thereby generating physical fail bit map data (hereinafter referred toas “detailed physical data”). This physical conversion section 126 isconstituted by dedicated hardware and can execute the physicalconversion processing at high speed.

[0058] In addition, the tester processing section 122 controls theentire semiconductor test device 100 in order to execute a test programwith an operating system (OS) to carry out a predetermined test. Forexample, processing for generating CFM data based upon AFM data isperformed by this tester processing section 122. The communicationcontrol section 124 performs transmission and reception of various datawith the fail analysis device 10 connected to the semiconductor testdevice 100.

[0059]FIG. 2 is a diagram showing a detailed structure of the failanalysis device 10 of this embodiment. As shown in FIG. 2, the failanalysis device 10 includes a communication control section 12, alogical map storage section 14, a physical conversion section 16, aphysical map storage section 18, a reduction processing section 20, adetailed data acquiring section 30, an acquisition range setting section32, a reduced data acquiring section 40, a main viewer generatingsection 80, a logical viewer generating section 82, a physical viewergenerating section 84, a layer control section 86, a display rangechanging sections 87, 186, an image synthesis section 88, a displaycontrol section 90, a display device 94, an operation section 96, and aGUI processing section 98.

[0060] The communication control section 12 performs transmission andreception of various data with the semiconductor test device 100. Thelogical map storage section 14 stores detailed logical data and reducedlogical data obtained by a test with respect to the DUT 130.

[0061] The physical conversion section 16 generates physical fail bitmap data (hereinafter referred to as “detailed physical data”) byperforming the physical conversion processing based upon the detailedlogical data. The physical map storage section 18 stores the detailedphysical data obtained by the physical conversion processing by thephysical conversion section 16. The reduction processing section 20performs reduction processing for generating bit map data obtained byreducing contents of the detailed physical data (hereinafter referred toas “reduced physical data”). This reduction processing is the same asthe processing in the case in which CFM data is generated from AFM datain the above-described semiconductor test device 100.

[0062] The detailed data acquiring section 30 acquires detailed logicaldata and detailed physical data. The fail analysis device 10 of thisembodiment has two kinds of analysis modes of a “tester mode” forperforming various kinds of analysis while acquiring the detailedlogical data and the reduced logical data directly from thesemiconductor test device 100 and a “file mode” for performing variouskinds of analysis based upon the detailed logical data or the likesaved.

[0063] More specifically, the detailed logical data is acquired byreading out the AFM data from the AFM 118 in the semiconductor testdevice 100 in the tester mode and is acquired by reading out applicabledata from the logical map storage section 14 in the file mode. In thetester mode, the detailed physical data is acquired by reading a resultof performing the physical conversion processing by the physicalconversion section 126 based upon the detailed logical data stored inthe AFM 118 in the semiconductor test device 100. In the file mode, thedetailed physical data is acquired by reading out applicable data fromthe physical map storage section 18.

[0064] The acquisition range setting section 32 sets acquisition rangesof the detailed logical data and the detailed physical data. In the failanalysis device 10 of this embodiment, separately from a display rangeof the detailed logical map or physical map, acquisition ranges (readingranges) of the detailed logical data and the detailed physical datalarger than this display range can be set. A specific setting methodwill be described later.

[0065] In addition, the reduced data acquiring section 40 acquiresreduced logical data and reduced physical data. More specifically, inthe tester mode, the reduced logical data is acquired by reading out CFMdata from the CFM 120 in the semiconductor test device 100 and in thefile mode, the reduced logical data is obtained by reading outapplicable data from the logical map storage section 14. In addition,the reduced physical data is acquired by performing reduction processingby the reduction processing section 20 based upon the detailed physicaldata acquired by the physical conversion processing in the tester mode,and in the file mode, the reduced physical data is acquired byperforming reduction processing by the reduction processing section 20based upon the detailed physical data read out from the physical mapstorage section 18.

[0066] The main viewer generating section 80 generates drawing datanecessary for displaying a main viewer window on the display device 94.Test results of the plurality of DUTs 130 which were objects of test areincluded in this main viewer window in a list form.

[0067] The logical viewer generating section 82 generates drawing datanecessary for displaying a logical viewer window on the display device94. A logical fail bit map at the time when a specific DUT 130 and I/Onumber are designated is included in this logical viewer window.

[0068] In addition, the physical viewer generating section 84 generatesdrawing data necessary for displaying a physical viewer window on thedisplay device 94. A physical fail bit map at the time when the specificDUT 130 is designated is included in this physical viewer window.Specific examples of the above-described main viewer window, logicalviewer window, and physical viewer window will be described later.

[0069] Incidentally, in the fail analysis device 10 of this embodiment,a plurality of logical maps or a plurality of physical maps can besuperimposed with each other and displayed, and a concept of layer forperforming such superimposition of images is introduced. Morespecifically, each of fail bit map images to be object ofsuperimposition is assigned with each of a plurality of layers to definerelationship among the layers.

[0070] The layer control section 86 controls contents of setting foreach layer and contents of relation among the respective layers. Settingof these pieces of information is performed using a layer windowdisplayed by the layer control section 86. A specific example of thelayer window will be described later.

[0071] When change of a display range such as move or zoom isinstructed, the display range changing section 87 performs change of adisplay range of superimposed all fail bit maps which are objects ofdisplay based upon control information set by the layer control section86. More specifically, the display range changing section 87 recognizesthe fail bit maps, which are superimposed at the point when theinstruction of change is given, based upon the control information and,at the same time, instructs the logical viewer generating section 82 orthe physical viewer generating section 84 to perform change of thedisplay range of these fail bit maps.

[0072] The image synthesis section 88 generates drawing data, which arenecessary for displaying an image obtained by superimposing logical mapsor physical maps with each other, based upon the control information setby the layer control section 86.

[0073] When change of a display range is instructed, the display rangechanging section 186 performs change of a display range of a fail bitmap displayed at that point. This display range changing section 186 isprovided with a move processing section 187 and a zoom processingsection 188.

[0074] When move of a display range is instructed, the move processingsection 187 moves a display range in accordance with this instruction ofmove. More specifically, the move processing section 187 determines amoving direction and a moving amount of the display range and instructsthe logical viewer generating section 82 or the physical viewergenerating section 84, which correspond to a window displayed at thatpoint, to generate a window including a moved and new logical map orphysical map.

[0075] When zoom of a display range is instructed, the zoom processingsection 188 enlarges (zooms out) or reduces (zooms in) the display rangein accordance with this zoom instruction. More specifically, the zoomprocessing section 188 determines a new display range and instructs thelogical viewer generating section 82 or the physical viewer generatingsection 84, which corresponds to a window displayed at that point, togenerate a window including a new logical map or physical map includedin this range.

[0076] The display control section 90 generates a video signal, which isoutputted to the display device 94, based upon drawing data generated byeach of the main viewer generating section 80, the logical viewergenerating section 82, the physical viewer generating section 84, andthe image synthesis section 88. This display control section 90 isprovided with a VRAM (video RAM) 92, in which drawing data of a windowwhich a user wishes to display at the top on a screen.

[0077] The operation section 96 is for a user to perform various inputsof instructions, and a mouse serving as a pointing device fordesignating an arbitrary position on a display screen of the displaydevice 94 and a keyboard consisting of ten keys, alphabet keys, orvarious symbol keys are included in the operation section 96. As thepointing device, a device other than the mouse, for example, an inputtablet, a touch panel, or the like may be used. The GUI (Graphical UserInterface) processing section 98 is a section for realizing GUIprocessing corresponding to an operation state of the operation section96. For example, when various commands and buttons included in a mainviewer window or the like are clicked using the mouse, the GUIprocessing section 98 judges what processing is specified and requestsexecution of corresponding processing.

[0078] In a specific example 1 of operations described below, thedetailed data acquiring section 30 and the reduced data acquiringsection 40 correspond to a test result acquiring unit, the main viewergenerating section 80 corresponds to a list image generation unit, theoperation section 96 and the GUI processing section 98 correspond to anoperation unit, the logical viewer generating section 82 and thephysical viewer generating section 84 correspond to a detailed imagegeneration unit, and the display control section 90 and the displaydevice 94 correspond to a display unit.

[0079] In addition, in a specific example 2 of operations, the detaileddata acquiring section 30 corresponds to a test result acquiring unit,the acquisition range setting section 32 corresponds to an acquisitionrange setting unit, the logical viewer generating section 82 and thephysical viewer generating section 84 correspond to a fail bit mapgenerating unit, the display control section 90 and the display device94 correspond to a display unit, the operation section 96 and the GUIprocessing section 98 correspond to an operation unit, and the displayrange changing section 186 corresponds to a display range changing unit.

[0080] In addition, in a specific example 3 of operations, the mainviewer generating section 80, the logical viewer generating section 82,and the physical viewer generating section 84 correspond to a fail bitmap generating unit, the layer control section 86 corresponds to a layercontrol unit, the display range changing section 87 corresponds to adisplay range changing unit, the image synthesis section 88 correspondsto an image superimposing unit, the display control section 90 and thedisplay section 94 correspond to a display unit, and the operationdevice 96 and the GUI processing section 98 correspond to an operationunit.

[0081] The fail analysis device 10 of this embodiment has such astructure, and operations thereof will be described next.

Specific Example 1 of Operations

[0082]FIG. 3 is a flow diagram showing operation procedures of a failanalysis device corresponding to a specific example 1 and shows a seriesof operation procedures for displaying a main viewer window in thetester mode.

[0083] When the fail analysis device 10 is started up, first, the mainviewer generating section 80 generates a screen of the main viewerwindow and displays it on the display device 94 (step 100).

[0084]FIG. 4 is a diagram showing a specific example of the main viewerwindow to be displayed after the fail analysis device 10 is started up.Each displayed content in the main viewer window will be hereinafterdescribed.

[0085] “Start MPAT” Button (a1)

[0086] This button is used for instructing the semiconductor test device100 connected to the fail analysis device 10 to start of a functionaltest of one or a plurality of DUTs 130 set therein and at the same timeinstructing the semiconductor test device 100 to capture AFM data andCFM data to be obtained by this functional test.

[0087] “Read” Button (a2)

[0088] In the case in which the functional test has already ended andfail data are stored in the AFM 118 and CFM 120, this button is used forinstructing the semiconductor test device 100 to read these fail data.When this button is depressed, the AFM data is acquired by the detaileddata acquiring section 30 and the CFM data is acquired by the reduceddata acquiring section 40.

[0089] DUT Designation Box and Push Button for Number Designation (a4)

[0090] These are used for designating a specific DUT 130 and changingDUT to be designated. A user can designate the specific DUT 130 bydirectly inputting a number in this box using ten keys provided in theoperation section 96. Alternatively, the user can designate the specificDUT 130 by operating the mouse provided in the operation section 96 todepress this push button for the necessary number of times. In order todisplay a fail map after changing the DUT number, the user needs todepress the above-described “Start MPAT” button a1 or “Read” button a2.

[0091] Origin Designation Toggle Buttons (a5)

[0092] These buttons are used for designating an origin. A user candesignate an arbitrary origin by depressing any of the four buttons. Inthe case in which a reduced image (described later) of a logical failbit map is included in the main viewer window, display is performedusing designated origin. In addition, in the case in which the logicalmap viewer window or the physical map viewer window is started up fromthe main viewer window, the logical map viewer window or the physicalmap viewer window is displayed using the designated origin.

[0093] Axis Change Push Button (a6)

[0094] This button is used for designating an X-axis and a Y-axis of afail bit map. Positive directions of the X-axis and the Y-axis arechanged each time this button is pressed. Note that, in the case inwhich the logical viewer window or the physical viewer window is startedup from the main viewer window, an origin designated here is used todisplay the logical map viewer window or the physical map viewer window.

[0095] DUT Data Display Area (a7)

[0096] This area is used for displaying a result image indicating a testresult of each of the plurality of DUTs 130 which were objects of thetest. A number included in each result image shown in a rectangularshape indicates a DUT number, and pass/fail of the DUT 130 specified bythis DUT number is represented by a color in this rectangle. Forexample, in the case of pass (in the case in which all reduced logicaldata corresponding to this DUT number are pass), the rectangle iscolored green and, in the case of fail (in the case in which at leastone of the reduced logical data corresponding to this DUT number isfail), the rectangle is colored red. Note that, although DUT numbers of1 to 128 are shown in the DUT data display area a7 shown in FIG. 4, inthe case in which the number of DUTs 130 actually implemented in thesemiconductor test device 100 is fewer than 128, numbers in rectanglesin which corresponding DUT 130 does not exist is not displayed orshadowed. When a notice is sent to the fail analysis device 10 from thesemiconductor test device 100, information on the number of the DUT 130and an I/O number to be described next is read and these numbers areupdated. In addition, in the case in which the number of DUTs 130actually implemented in the semiconductor test device 100 exceeds 128,pages in which result images of the 128 DUTs 130 are included areswitched to be displayed.

[0097] I/O Data Display Area (a8)

[0098] This area is used for displaying a test image showing a testresult for each I/O number concerning a specific DUT 130 for which a DUTnumber is designated. A number included in each result image shown in arectangular shape indicates an I/O number, pass/fail of a logical failbit map designated by this I/O number is represented by a color in thisrectangle. For example, in the case of pass (in the case in which allreduced logical data corresponding to this I/O number are pass), therectangle is colored green and, in the case of fail (in the case inwhich at least one of the reduced logical data corresponding to this I/Onumber is fail), the rectangle is colored red. Note that, although I/Onumbers of 0 to 143 are shown in the I/O data display area a8 shown inFIG. 4, in the case in which a maximum value of the I/O number of DUTs130 actually implemented in the semiconductor test device 100 is fewerthan 143, numbers in rectangles in which corresponding I/O number doesnot exist is not displayed or shadowed. In addition, in the case inwhich the maximum value of I/O numbers exceeds 143, the numbers aredisplayed by switching pages.

[0099] Display Switching Option Menu (a9)

[0100] This menu is used for switching displayed contents in theabove-described DUT data display area a7 or I/O data display area a8.For the DUT data display area a7, display options of “Pass/Fail”, “CFM(All)”, “CFM (16DUT)”, and “CFM (32DUT)” are prepared. In addition, forthe I/O data display area 8a, display options of “Pass/Fail”, “CFM(All)”, “CFM (16 or 18 I/O)”, and “CFM (32 or 36 I/O)” are prepared.

[0101] “Pass/Fail” is an option for displaying the above-describedresult image indicating pass/fail of a test result. In an initial screenof the main viewer window shown in FIG. 4, a state in which this displayoption is selected as default at the start-up time is shown.

[0102] In addition, each of “CFM (All)”, “CFM (16 DUT)”, “CFM (32 DUT)”,“CFM (16 or 18 I/O)”, and “CFM (32 or 36 I/O)” is an option fordisplaying reduced images showing logical fail bit maps corresponding toreduced logical data (hereinafter referred to as “reduced logical map”)by a number in parentheses. A specific display example of the reducedimage will be described later.

[0103] “Physical” Button (a10)

[0104] This button is used for instructing display of a physical viewerwindow corresponding to a specific DUT 130 for which a DUT number isdesignated.

[0105] In a state in which the main viewer window shown in FIG. 4 isdisplayed, then, the GUI processing section 98 judges whether or not adisplay option has been changed (step 101), whether or not a DUT numberhas been changed (step 102), whether or not an I/O number has beendesignated (step 103), and whether or not physical conversion has beeninstructed (step 104).

[0106] All the display options other than “Pass/Fail” included in thedisplay switching option menu are options for displaying a list ofreduced logical maps. If these display options are selected, affirmativejudgment is made in the judgment of step 101 and, next, based upon thechanged display option, the main viewer generating section 80 changesdisplayed contents of the main viewer window (step 105).

[0107]FIG. 5 is a diagram showing a specific example of the main viewerwindow in which a list of reduced images showing reduced logical maps isincluded. For example, a state in which “CFM (16 DUT)” is selected as adisplay option corresponding to the DUT data display area a7 and “CFM(16 or 18 I/O)” is selected as a display option corresponding to the I/Odata display area a8 is shown.

[0108] In the DUT data display area a7, a rectangular area in which anumber is included has the same contents as in the case in which“Pass/Fail” is selected as a display option, and corresponds to a resultimage showing pass/fail of the DUT 130 designated by this number. Arectangular area located above it shows a reduced image showing contentsof a reduced logical map for each DUT 130. Since CFM data (reducedlogical data) for each I/O number is read out from the CFM 120 in thesemiconductor test device 100, the main viewer generating section 80finds OR of each bit of reduced logical data of all the I/O numbers foreach DUT 130 to generate this reduced image.

[0109] In addition, in the I/O data display area a8, a rectangular areain which a number is included has the same contents as in the case inwhich “Pass/Fail” is selected as a display option, and corresponds to aresult image indicating pass/fail of reduced logical data of the I/Onumber. A rectangular area located above it shows a reduced imageshowing contents of a reduced logical map for each I/O number.

[0110] Note that, although both the DUT data display area a7 and the I/Odata display area a8 are displayed in the example shown in FIG. 5, it isalso possible to bring one of them into a non-display state and increasethe number of displayable data of the other. FIG. 6 is a diagram showinga specific example of the main viewer window in the case in which theDUT data display area a7 is brought into the non-display state and, atthe same time, “CFM (All)” is selected as a display option of the I/Odata display area a8.

[0111] In addition, in a state in which the main viewer window isdisplayed, when a DUT number selected at that point is changed,affirmative judgment is made in the judgment of step 102, and then themain viewer generating section 80 performs change of displayed contentsof the I/O data display area a8 corresponding to a DUT number afterchange (step 106).

[0112] Further, in the state in which the main viewer window isdisplayed, when any I/O number included in the I/O data display area a8is designated, affirmative judgment is made in the judgment of step 103,and then the logical viewer generating section 82 generates a screen ofthe logical viewer window corresponding to this designated I/O numberand displays it on the display device 94 (step 107).

[0113]FIG. 7 is a diagram showing a specific example of the logicalviewer window. A reduced logical map a11 and a logical fail bit map a12corresponding to a part or all of the reduced logical map a11 areincluded in this window. This logical fail bit map a12 is generatedbased upon detailed logical data acquired by the detailed data acquiringsection 30.

[0114] In addition, in the state in which the main viewer window isdisplayed, when the “Physical” button a10 is selected, affirmativejudgment is made in the judgment of step 104, and then the physicalviewer generating section 84 generates a screen of the physical viewerwindow corresponding to the DUT number designated at that point anddisplays it on the display device 94 (step 108).

[0115]FIG. 8 is a diagram showing a specific example of the physicalviewer window. A reduced physical map a13 and a physical fail bit mapa14 corresponding to a part or all of the reduced logical map a13 areincluded in this window. This physical fail bit map a14 is generatedbased upon detailed logical data acquired by the detailed data acquiringsection 30.

[0116] In this way, in the fail analysis device 10 of this embodiment,since test results corresponding to the plurality of DUTs 130 aredisplayed as a list in the main viewer window, a user can easily graspan outline of fail information of each DUT 130. In particular, since theuser can easily grasp presence or absence of fail according to list ofresult images and can learn a general distribution state of failaccording to a list of reduced images of a fail bit map, the user cansurely grasp an outline of fail information for each DUT 130 or each I/Onumber.

[0117] In addition, simply by designating any of list images (resultimages or reduced images) included in the main viewer window, a logicalviewer window or a physical viewer window corresponding to the image canbe displayed. Consequently, in the case in which a user would like toconfirm the detailed contents after he/she looks over the list images,troublesome labors, which are required until contents of a detailed failbit map corresponding to a specific DUT 130 or a specific I/O number areactually confirmed, are reduced, and simplification of operationsbecomes possible. In addition, in accordance with the simplification ofoperations, reduction of a time required to operate also becomespossible.

[0118] In particular, since the reduced logical data (CFM data)necessary for display a list of reduced images included in the mainviewer window is generated in the semiconductor test device 100, itbecomes possible to reduce time until the main viewer window includingsuch a list of reduced images is displayed.

Specific Example 2 of Operations

[0119]FIG. 9 is a flow diagram showing operation procedures of a failanalysis device corresponding to a specific example 2 and mainly showsoperation procedures in the case in which a range of acquiring detailedlogical data or detailed physical data is acquired by the detailed dataacquiring section 30 is variably set and change of a display range isinstructed while a logical viewer window or a physical viewer window isdisplayed.

[0120] When the fail analysis device 10 is started up, first, the manviewer generating section 80 generates a screen of the main viewerwindow shown in FIG. 4 and displays it on the display section 94 (step200).

[0121] In a state in which the main viewer window shown in FIG. 4 isdisplayed, next, the GUI processing section 98 judges whether or notdisplay of a page size menu has been instructed (step 201). Here, a pagesize indicates a range of acquiring data by the detailed data acquiringsection 30 set by the acquisition range setting section 32. For example,it is assumed that an item “Page Size” is included in a pull down menucorresponding to “View” in a menu bar displayed in the upper part of themain viewer window. The GUI processing section 98 watches whether or notthis item “Page Size” has been clicked by the mouse or pointed using thekeyboard, thereby performing the above-described judgment of step 201.

[0122] If display of the page size menu is instructed, affirmativejudgment is made in the judgment of step 201, and then the acquisitionrange setting section 32 performs setting of a page size using the pagesize menu which is displayed in accordance with this instruction (step202).

[0123]FIG. 10 is a diagram showing a specific example of the page sizemenu. Sizes of fail bit maps which can be acquired by one readingoperation by the detailed data acquiring section 30 are listed in thepage size menu. More specifically, as shown in FIG. 10, seven sizes of128 (X address)×128 (Y address), 256×256, . . . , and 8192×8192 andtotal eleven kinds of options of “Auto” for automatically setting andchanging the page size according to a size of a display range areincluded in the page size menu P. If “Auto” is selected, a size of asquare of a length of minimum power of 2 exceeding a size of a longeraddress of the display range is set as the page size.

[0124] Next, the GUI processing section 98 judges whether or not displayof the logical viewer window or the physical viewer window has beeninstructed (step 203).

[0125] In a state in which the main viewer window is displayed, when anyI/O number included in the I/O data display area a8 is designated, thismeans that display of the logical viewer window is instructed. In thiscase, affirmative judgment is made in the judgment of step 203, and thenthe detailed data acquiring section 30 acquires detailed logical datafor the page size set by the acquisition range setting section 32 instep 202 (step 204). The logical viewer generating section 82 generatesa screen of the logical viewer window (FIG. 7) corresponding to thedesignated I/O number based upon the detailed logical data or the likeacquired by the detailed data acquiring section 30 and displays it onthe display section 94 (step 205).

[0126] In addition, in the state in which the main viewer window isdisplayed, when the “Physical” button a10 is selected, this means thatdisplay of the physical viewer window is instructed. In this case,again, affirmative judgment is made in the judgment of step 203, andthen the detailed data acquiring section 30 acquires detailed physicaldata for the page size set by the acquisition range setting section 32in step 202 (step 204). The physical viewer generating section 84generates a screen of the physical viewer window (FIG. 8) correspondingto the DUT number designated at that time based upon the detailedphysical data or the like acquired by the detailed data acquiringsection 30 and displays it on the display section 94 (step 205).

[0127] Next, the GUI processing section 98 judges whether or not move orzoom of a display range of a fail bit map being displayed has beeninstructed (step 206). In a state in which the logical viewer window orthe physical viewer window is displayed, if move or zoom of a displayrange is instructed using the mouse of the operation section 96,affirmative judgment is made in the judgment of step 206. For example, auser drags the display range while pressing the left button of the mouseon the reduced logical map a11 included in the logical viewer window,whereby zoom processing with respect to the dragged range is instructed.Alternatively, the user drags the display range while pressing thecentral button of the mouse on the reduced logical map a11, whereby moveof the display range in the dragged direction without change of adisplay magnification is instructed. This is true for the case in whichmove or zoom of the display range is instructed in a state in which thephysical viewer window is displayed.

[0128] Next, the acquisition range setting section 32 judges whether ornot the display range after change is included in the acquisition rangeof data by the detailed data acquiring section 30 (step 207). If thedisplay range is not included in the acquisition range of data, negativejudgment is made, and then the detailed data acquiring section 30performs reacquisition of data corresponding to a window to be displayed(step 208). For example, if move or zoom is instructed when the logicalviewer window is displayed, acquisition of detailed logical data isperformed. In addition, if move or zoom is instructed when the physicalviewer window is displayed, acquisition of detailed physical data isperformed.

[0129] When the display range after change is within the acquisitionrange of data and affirmative judgment is made in the judgment of step206, or after reacquisition of data is performed in step 208, the moveprocessing section 187 or the zoom processing section 188 in the displayrange changing section 186 sends an instruction to the logical viewergenerating section 82 or the physical viewer generating section 84 toperform setting of a present display range. Consequently, displayedcontents are changed (step 209). Thereafter, the fail analysis devicereturns to step 206 and the processing is repeated.

[0130]FIG. 11 is a diagram showing a relation between a display rangeand an acquisition range of data. For example, a correspondence relationbetween the reduced logical map a11 included in the logical viewerwindow and the detailed logical fail bit map a12 is shown. Note thatthis is true for the case in which the physical viewer window is used,and a specific example of operation instruction using the logical viewerwindow will be described in the following description.

[0131] As shown in FIG. 11, an acquisition frame c indicating theacquisition range of data at that point and a display frame b1indicating a drawing range of the logical fail bit map a11, which is adisplay range, at that point are included in an image of the reducedlogical map a11 in the logical viewer window. In the fail analysisdevice 10 of this embodiment, the acquisition frame c larger than thedisplay frame b1 is set. In addition, an instruction of move or zoom ofthe display range is given using the reduced logical map a11 in whichthe display frame b1 and the acquisition frame c are displayed.

[0132]FIG. 12 is a diagram showing a specific example of a moveinstruction using the reduced logical map a11. As shown in FIG. 12, auser operates the mouse to designate an arbitrary position d1 in thedisplay frame b1 and, while pressing the central button of the mouse inthis state, drags the display range in a direction and to a position asindicated by arrow e1 in the drawing. Consequently, the user can move adisplay range b1 to a display range b2. In addition, in accordance withthis move operation, displayed contents of the logical fail bit map a12in the logical viewer window change continuously.

[0133]FIG. 13 is a diagram showing a specific example of a zoominstruction using the reduced logical map a11. As shown in FIG. 13, auser operates the mouse to designate an arbitrary position d2 in thedisplay frame b1 and, while pressing the left button of the mouse inthis state, drags the display range in a direction and to a position asindicated by arrow e2 in the drawing. Consequently, zoom-up processingfor changing the display range b1 to the display range b3 can beperformed. Note that, in the case in which the display range b2 afterthe operation is smaller than the display range b1 before the operation,zoom-in processing is performed.

[0134] In this way, in the fail analysis device of this embodiment, arange in which detailed logical map data or detailed physical map dataas a test result is acquired is made larger than a display range of adetailed logical map or physical map. Thus, in performing move or zoomof the display range of the detailed logical map or the detailedphysical map, the user does not need to perform reacquisition of data inthe case in which move or zoom is performed in the acquisition range ofdata. Therefore, time required since change of a display range isinstructed until the display range is actually changed can be reduced.

[0135] In addition, in the case in which the page size, which is theacquisition range of data, is set to “Auto”, if the display range of thedetailed logical map or the like is large, the acquisition range of datais also set large and, to the contrary, if the display range is small,the acquisition range of data is also set small. Thus, waste ofacquiring data even for a range almost unnecessary for display can becut down, and the most suitable processing of the fail analysis devicetaking into account processing capability and the like becomes possible.

[0136] In addition, in the case in which the display range is moved orzoomed, since it is sufficient to perform reacquisition of data only ifthe display range exceeds the acquisition range of data, the number oftimes of this reacquisition can be minimized.

[0137] Further, the reduced logical map a11 and the detailed logicalfail bit map a12 are included in the logical viewer window and a usercan perform an instruction operation of move or zoom of the displayrange using this reduced logical map a11, the user does not need toswitch to a detailed display screen after roughly confirming contents ona reduced display screen as in the past, and operability in giving aninstruction of switching can be improved. This is true for the case inwhich the physical viewer window is used.

[0138] In particular, since the user can perform designation of a newdisplay range by designating two points in the reduced logical map a11or the reduced physical map a13 using a pointing device such as a mouseand dragging the display range between the two points, the user canperform designation of a range of zoom-in or zoom-out easily and withthe same operation procedures. In addition, since the user can performdesignation of a new display range by designating an arbitrary one pointin the reduced logical map a11 or the reduced physical map a13, a movingdirection, and a moving amount, the user can easily give an instructionto move the display range.

[0139] Further, since the user can give an instruction of move or zoomof the display range while confirming the acquisition range of data byincluding the display frame b1 and the acquisition frame c in an imageof the reduced logical map a11 or the like, for which an operationinstruction of move or zoom is performed, it becomes possible to givethese instructions within the acquisition range of data.

Specific Example 3 of Operations

[0140]FIG. 14 is a flow diagram showing operation procedures of a failanalysis device corresponding to a specific example 3 and mainly showsoperation procedures in the case in which various setting contents setby using a layer window are reflected on display and a display range ofsuperimposed images is changed.

[0141] When the fail analysis device 10 is started up, the layer controlsection 86 judges whether or not a logical viewer window or a physicalviewer window is displayed (step 300).

[0142] For example, the logical viewer window or the physical viewerwindow can be displayed by performing a predetermined operation in astate in which a main viewer window is displayed. Next, a specificmethod in the case in which the logical viewer window or the physicalviewer window is started up from the main viewer window will bedescribed.

[0143] As described above, a specific example of the main viewer windowto be displayed after the fail analysis device 10 is started up is shownin FIG. 4. In addition, a specific example of the main viewer window inwhich a list of reduced images showing a reduced logical map is includedis shown in FIG. 5. Further, a specific example of the logical viewerwindow is shown in FIG. 7 and a specific example of the physical viewerwindow is shown in FIG. 8.

[0144] Note that, although both the DUT data display area a7 and the I/Odata display area a8 are displayed in the example shown in FIG. 5, it isalso possible to bring one of them into a non-display state and increasethe number of displayable data of the other (FIG. 6).

[0145] When any I/O number included in the I/O data display area a8 isdesignated in a state in which the above-described main viewer window isdisplayed, this means that display of the logical viewer window isinstructed.

[0146] In addition, when the “Physical” button a10 is selected in thestate in which the main viewer window is displayed, this means thatdisplay of the physical viewer window is instructed.

[0147] When the logical viewer window or the physical viewer window isdisplayed in this way, affirmative judgment is made in the judgment ofstep 300, and then the GUI processing section 98 judges whether or notdisplay of the layer window is instructed (step 301). For example, it isassumed that an item “Layers . . . ” for instruction display of thelayer window is included in a pull down menu corresponding to “View” ina menu bar displayed in the upper part of the logical viewer window orthe physical viewer window in display. The GUI processing section 98watches whether or not this item “Layers . . . ” has been clicked by themouse or pointed using the keyboard, thereby performing theabove-described judgment of step 301.

[0148] If display of the layer window is not instructed, negativejudgment is performed in the judgment of step 301, and then the GUIprocessing section 98 judges whether or not change of a display range ofa fail bit map being displayed has been instructed (step 302). If changeof the display range is not instructed, the fail analysis device returnsto step 300 and the processing is repeated.

[0149] In addition, if display of the layer window is instructed,affirmative judgment is made in the judgment of step 301, and then thelayer control section 86 generates an image of the layer window anddisplays it on the display section 94 (step 303).

[0150]FIG. 15 is a diagram showing a specific example of the layerwindow. A layer display area b1 and a button area b2 are included inthis window. When a user operates the mouse to click a layer name(“Layer 0”, etc.) included in the layer display area b1, a part wherethis layer is shown turns into reversal display, and a logical viewerwindow or a physical viewer window corresponding to this layer becomesoperable. A fail color designation box c1 is used for, in the case inwhich a fail part is included in a fail bit map corresponding to thelayer, designating a color of the fail part. The color of the fail partcan be set arbitrarily using this fail color designation box c1 becausea fail distribution of each fail bit map becomes unclear if all failparts of fail bit maps to be superimposed are colored in the same color.A check button c2 is a button for designating a layer to be an object ofprocessing in the case in which processing corresponding to variousbuttons included in the button area b1 is performed. A visible displaymark c3 and an invisible mark c4 set a display state of a logical map ora physical map corresponding to the layer and indicate contents of theset display state. Display of these marks is switched every time a useroperates the mouse to click the marks.

[0151] In addition, the button area b2 includes a plurality of buttonsfor designating various contents of processing with respect to a logicalviewer window or the like corresponding to each layer. A “New” button isused for instructing addition of a new layer. A display position of alayer to be added is the top (forefront). A “Del” button is used fordeleting a selected (reversely displayed) layer. An “Or” button is abutton for instructing execution of an OR operation using various failbit maps corresponding to a selected layer. An “And” button is a buttonfor instructing execution of an AND operation using various fail bitmaps corresponding to a selected layer. An “Xor” button is a button forinstructing execution of an exclusive OR operation using a fail bit mapcorresponding to each of two layers. In the case in which three or morelayers are selected, top two layers are automatically selected. A “Not”is a button for instructing execution of a logical NOT operation withrespect to each of various fail bit maps corresponding to a selectedlayer.

[0152] In a state in which the above-described layer window isdisplayed, the GUI processing section 98 judges whether or not any itemcontent included in the layer window is changed (step 304). If the layerwindow is closed without any change, negative judgment is made, and theabove-described judgment processing of step 300 is repeated.

[0153] If any item content in the layer window is changed, affirmativejudgment is made in the judgment of step 304, and the logical viewergenerating section 82 or the physical viewer generating section 84performs display reflecting this changed item content (step 305). Afterthis display processing is performed, the fail analysis device returnsto step 300 and the processing is repeated.

[0154] Further, in a state in which a logical viewer window or aphysical viewer window is displayed, in the case in which change of adisplay range is instructed using the mouse, affirmative judgment ismade in the judgment of step 302. For example, a user drags the displayrange while pressing the left button of the mouse on the reduced logicalmap a11 included in the logical viewer window, whereby zoom processingwith respect to the dragged range is instructed. Alternatively, the userdrags the display range while pressing the central button of the mouseon the reduced logical map a11, whereby move processing of the displayrange in the dragged direction without change of a display magnificationis instructed. This is true for the case in which change of the displayrange is instructed in a state in which the physical viewer window isdisplayed.

[0155] Next, the display range changing section 87 sends an instructionto the logical viewer generating section 82 or the physical viewergenerating section 84 to perform change of a present display range (step306). Thereafter, the fail analysis device returns to step 300 and theprocessing is repeated.

[0156]FIG. 16 is a diagram showing a specific example of superimpositionof fail bit maps. For example, it is assumed that fail bit maps ofdifferent contents are correspondent to each of a layer 0, a layer 1,and a layer 2. Note that, description is made with the case in whichlogical fail bit maps are superimposed as an example in the followingdescription, the same is true for physical fail bit maps.

[0157] In this case, contents of the reduced logical map a11 and thelogical fail bit map a12 of the logical viewer window shown in FIG. 7are contents of superimposed three fail bit maps corresponding to thesethree layers 0, 1, and 2. In this case, if different colors are set foreach layer using the fail color designation box cl included in the layerdisplay area b1 of the layer window, different colors are given to failparts of the respective fail bit maps. In the case in which if there isa layer in which the invisible mark c4 is set and non-display is set inthe layer display area b1 of the layer window, as shown in FIG. 17, thefail bit map corresponding to this layer is not used for superimpositionof images.

[0158] Note that an order of superimposition of the fail bit mapscorresponding to the respective layers corresponds to layer numbers. Forexample, the layer 0 is the lowermost layer, a layer having the largerlayer number is an upper layer, and the largest layer number correspondsto the layer in the forefront. Therefore, the order of superimpositioncan be changed easily by changing the layer numbers. Change of the layernumbers is performed by clicking an arrow button, which is arranged inthe vicinity of the right end of the button area b2 of the layer window,with a mouse. When the user desires to change an order ofsuperimposition of a fail bit map, which corresponds to a layer reversedin the layer display area b1, to an immediately higher or lower order,the user only has to click an upward arrow button or a downward arrowbutton once.

[0159]FIG. 18 is a diagram showing another specific example ofsuperimposition of fail bit maps and shows an outline in the case inwhich zoom processing is performed to change a display range. Variousoperations using the logical viewer window becomes possible with respectto a layer (e.g., the layer 1) reversed in the layer display area b1 ofthe layer window. However, in this embodiment, in the case in which thezoom processing is instructed using the reduced logical map a11 in thelogical viewer window, the zoom processing is performed simultaneouslynot only for a logical map corresponding to the layer 1 but also forrespective logical maps corresponding to the other layers 0 and 2related by using the layer window. As a result, an image obtained bysuperimposing images, which are logical maps corresponding to therespective layers 0, 1, and 2 individually subjected to the zoomprocessing, is displayed in the logical viewer window after executingthe zoom processing.

[0160]FIG. 19 is a diagram showing another specific example ofsuperimposition of fail bit maps and shows an outline in the case inwhich a display range is changed by performing move processing. In thecase in which the move processing is instructed using the reducedlogical map a11 in the logical viewer window, the move processing isperformed simultaneously not only for a logical map corresponding to thelayer 1 but also for respective logical maps corresponding to the otherlayers 0 and 2 related by using the layer window. As a result, an imageobtained by superimposing images, which are logical maps correspondingto the respective layers 0, 1, and 2 individually subjected to the moveprocessing, is displayed in the logical viewer window after executingthe move processing.

[0161]FIG. 20 is a diagram showing another specific example ofsuperimposition of fail bit maps. It is assumed that an image unrelatedto a test result of a fail bit map or the like is included in any onelayers, for example. FIG. 20 shows an outline in the case in whichsuperimposition of the images of the plurality of the layers includingthe above one layer is performed. As the image not relating to a testresult, for example, images such as a predetermined frame, ruled lines,letters, or the like are possible. In the example shown in FIG. 20, animage including a frame and a letters of “test result” is related to thelayer 4 to be arranged at the top, and this image and images of therespective fail bit maps are superimposed. Consequently, legibility ofdisplayed contents, or the like can be improved.

[0162] In this way, in the fail analysis device of this embodiment, eachof the superimposed plurality of fail bit map images corresponds to aplurality of layers, and relationship among the layers is defined usingthe layer window. Thus, in the case in which zoom processing or moveprocessing is performed, a user can change displayed contents whilemaintaining a mutual relation of the respective fail bit map images.Consequently, the user does not need to instruct the zoom processing orthe move processing individually with respect to the respective fail bitmap images, and operations can be simplified significantly.

[0163] Further, to turn off or redisplay for each of the superimposedfail bit maps, the user only has to switch the visible display mark c3and the invisible mark c4 in the layer window. Consequently, it becomesunnecessary to repeat reading of data and drawing processing each time,simplification of processing and operations becomes possible.

[0164] Moreover, when relationship among the respective layers isdefined using the layer window, since contents of a logical operationcan be set, a logical operation targeting each fail bit map becomespossible in accordance with the set contents.

Industrial Applicability

[0165] As described above, according to the present invention, testresults corresponding to a plurality of semiconductor memories aredisplayed in one screen. Therefore, it becomes easy to grasp an outlineof fail information concerning each semiconductor memory. In addition,trouble some labors, which are required until contents of a detailedfail bit map corresponding to a semiconductor memory including the failpart or an I/O number are confirmed, are reduced, and simplification ofoperations becomes possible.

[0166] Further, according to the present invention, since a range inwhich a test result is acquired is set as a first range larger than asecond range which is a display range, a user does not need to acquirethe test result again in changing the display range within the firstrange. Therefore, time required since change of the display range isinstructed until the display range is actually changed can be reduced.

[0167] Furthermore, a reduced image and a detailed image are bothincluded in an identical screen. Therefore, the user can designatechange of a display range using the reduced image. The user does notneed to switch to a detailed display screen after roughly confirmingcontents on a reduced display screen as in the past, and operability ingiving a switching instruction can be improved.

[0168] Moreover, since each of a superimposed plurality of fail bit mapimages is correspondent to a plurality of layers and relationship amongthe respective layers is defined, in the case in which a user performschange of contents of a display image, the user can change the displayedcontents while maintaining a mutual relation among the respective failbit map images. Consequently, the user does not need to give a moveinstruction individually or give an instruction to change a displaymagnification for each fail bit map image, and operations can besimplified significantly.

1. A fail analysis device for displaying results of testing a pluralityof semiconductor memories with a semiconductor test device, comprising:a test result acquiring unit for acquiring test results corresponding tosaid plurality of semiconductor memories; a list image generation unitfor generating a list image in which the test results corresponding tosaid plurality of semiconductor memories, which are acquired by saidtest result acquiring unit, are included in one screen; and a displayunit for displaying said list image generated by said list imagegeneration unit.
 2. The fail analysis device according to claim 1,characterized in that a result image indicating pass/fail for each ofsaid plurality of semiconductor memories is included in said list imageas said test result.
 3. The fail analysis device according to claim 1,characterized in that a reduced image of a fail bit map is included foreach of said plurality of semiconductor memories in said list image assaid test result.
 4. The fail analysis device according to claim 2,further comprising: an operation unit for designating any position insaid list image displayed on said display unit; and a detailed imagegeneration unit for, when any of said result images is designated bysaid operation unit, generating a detailed image of a fail bit mapcorresponding to the result image, characterized in that said detailedimage generated by said detailed image generation unit is displayed bysaid display unit.
 5. The fail analysis device according to claim 3,further comprising: an operation unit for designating any position insaid list image displayed on said display unit; and a detailed imagegeneration unit for, when any of said reduced images is designated bysaid operation unit, generating a detailed image of a fail bit mapcorresponding to the reduced image, characterized in that said detailedimage generated by said detailed image generation unit is displayed bysaid display unit.
 6. The fail analysis device according to claim 3,characterized in that said semiconductor test device generates a reducedfail bit map data necessary for displaying said reduced image, and saidlist image generation unit generates said reduced image based upon saidreduced fail bit map data.
 7. A fail analysis device for displaying aresult of testing a semiconductor memory with a semiconductor testdevice, comprising: a test result acquiring unit for acquiring a testresult corresponding to said semiconductor memory; a list imagegeneration unit for generating a list image in which a test result foreach I/O number of said semiconductor memory, which is acquired by saidtest result acquiring unit, is included in one screen; and a displayunit for displaying said list image generated by said list imagegeneration unit.
 8. The fail analysis device according to claim 7,characterized in that a result image indicating pass/fail for each saidI/O number is included in said list image as said test result.
 9. Thefail analysis device according to claim 8, characterized in that areduced image of a fail bit map is included for each said I/O number insaid list image as said test result.
 10. The fail analysis deviceaccording to claim 8, further comprising: an operation unit fordesignating any position in said list image displayed on said displayunit; and a detailed image generation unit for, when any of said resultimages is designated by said operation unit, generating a detailed imageof a fail bit map corresponding to the result image, characterized inthat said detailed image generated by said detailed image generationunit is displayed by said display unit.
 11. The fail analysis deviceaccording to claim 9, further comprising: an operation unit fordesignating any position in said list image displayed on said displayunit; and a detailed image generation unit for, when any of said reducedimages is designated by said operation unit, generating a detailed imageof a fail bit map corresponding to the reduced image, characterized inthat said detailed image generated by said detailed image generationunit is displayed by said display unit.
 12. The fail analysis deviceaccording to claim 9, characterized in that said semiconductor testdevice generates a reduced fail bit map data necessary for displayingsaid reduced image, and said list image generation unit generates saidreduced image based upon said reduced fail bit map data.
 13. A failanalysis device for displaying a result of testing a semiconductormemory with a semiconductor test device, comprising: a test resultacquiring unit for acquiring a test result of said semiconductor memoryenabling generation of a fail bit map of a first range; a fail bit mapgeneration unit for generating an image of a fail bit map of a secondrange narrower than said first range using a part of said test resultacquired by said test result acquiring unit; a display unit fordisplaying said image generated by said fail bit map generation unit; anoperation unit for instructing a display range of said fail bit map; anda display range changing unit for changing said display range using saidtest result acquired by said test result acquiring unit when change ofsaid display range is instructed within said first range by saidoperation unit.
 14. The fail analysis device according to claim 13,characterized by comprising an acquisition range setting unit forvariably setting a size of said first range according to a size of saiddisplay range instructed by said operation unit.
 15. The fail analysisdevice according to claim 13, characterized in that said test resultacquiring unit performs reacquisition of the test result of saidsemiconductor memory when change of said display range exceeding saidfirst range is instructed by said operation unit.
 16. A fail analysisdevice for displaying a result of testing a semiconductor memory with asemiconductor test device, comprising: a test result acquiring unit foracquiring a test result of said semiconductor memory; a fail bit mapgeneration unit for generating a first image of a fail bit map and asecond image of a reduced predetermined range including the vicinity ofsaid first image using said test result acquired by said test resultacquiring unit; a display unit for displaying said first image and saidsecond image in one screen; an operation unit for instructing change ofa display range of said fail bit map corresponding to said first imageusing said second image; and a display range changing unit for changingdisplayed contents of said first image when change of said display rangeis instructed by said operation unit.
 17. The fail analysis deviceaccording to claim 16, characterized in that said operation unit is apointing device capable of designating an arbitrary position on adisplay screen, and by designating two points in said second image withthe pointing device, a rectangular area with these two points asopposite angles is designated as said display range after change. 18.The fail analysis device according to claim 16, characterized in thatsaid operation unit is a pointing device capable of designating anarbitrary position on a display screen, and after designating one pointin said second image with the pointing device, move of the display rangeis instructed by designating a moving direction and a moving amount. 19.The fail analysis device according to claim 16, characterized in that anacquisition frame indicating a range of said test result acquired bysaid test result acquiring unit and a display frame indicating a drawingrange of said first image are included in said second image.
 20. Thefail analysis device according to claim 19, characterized in that saidtest result acquiring unit performs reacquisition of said test result ofsaid semiconductor memory when change of said display range exceedingsaid acquisition frame is instructed by said operation unit.
 21. A failanalysis device for displaying a result of testing a semiconductormemory with a semiconductor test device, comprising: a fail bit mapgeneration unit for generating a plurality of fail bit map imagesrepresenting a test result corresponding to said semiconductor memory; alayer control unit for assigning each of said plurality of fail bit mapimages to a plurality of layers and, at the same time, definingrelationship among the respective layers; an image superimposing unitfor performing processing for superimposing said plurality of fail bitmap images defined the relationship among said plurality of layers bysaid layer control unit; and a display unit for displaying the imagessuperimposed by said image superimposing unit.
 22. The fail analysisdevice according to claim 21, characterized in that said layer controlunit controls a display/non-display state of a fail bit map image foreach said layer.
 23. The fail analysis device according to claim 21,characterized in that said layer control unit sets contents of a logicaloperation targeting each of said plurality of layers according to saidrelation.
 24. The fail analysis device according to claim 21,characterized by further comprising: an operation unit for instructingchange of a display range of said fail bit map; and a display rangechanging unit for, when change of said display range is instructed bysaid operation unit, executing change of said display range targetingsaid plurality of fail bit maps corresponding to said plurality oflayers assigned by said layer control unit.
 25. The fail analysis deviceaccording to claim 21, characterized in that said layer control unitdefines said relationship by assigning images including images notrelating to said test result other than said plurality of fail bit mapimages to each of said plurality of layers.